DSP-based ATM SAR

ATM AAL5 SAR and Development Kit for Texas Instruments TMS320C6415 and TMS320C6416 DSPs

Intelligraphics, a leading developer of firmware, drivers and low-level systems software, provides a algorithm-based ATM Segmentation and Reassembly (SAR) module and ATM Development Kit for Texas Instruments' C6415 and C6416 DSP devices. This ATM SAR and Development Kit enables devices using the C64x platform to implement ATM communications functionality on the DSP. With high performance and a minimum processor load, the Intelligraphics ATM SAR and Development Kit provides a superior, low cost ATM solution.

The ATM SAR and Development Kit includes a full ATM stack, including AAL5 SAR, ATM layer, and physical layer library. A development API allows manufacturers to add their own ATM operation and management functions to the software libraries.

General Features

• Targeted for the Texas Instruments TMS320C6415 and TMS320C6416 fixed point digital signal processors
• Provides ATM functionality via the TMS320C6415 and TMS320C6416 Universal Test and Operations PHY Interface for ATM (UTOPIA) interface
• Combines ATM, AAL-5 and PCI DMA controller functionality in a DSP via firmware
• Supports configuration of Virtual Channels (VCs), allowing over 256 VCs
• Provides high performance SAR operations with a minimum processor load
• DSP-BIOS independent solution
• Conforms to Texas Instruments' eXpressDSP Algorithm Interoperability Standard (XDAIS)

ATM Adaptation Layer 5 (AAL5) Features

• Supports simultaneous segmentation and reassembly, configurable to 128 open virtual circuits in both directions
• Provides internal virtual circuit parameter storage for a configurable number of transmit and receive virtual circuits, enabling a high data throughput rate
• Includes optimized CRC generation and verification routines
• Provides configurable transmit, receive and reassembly buffering
• Supports configurable error handling and logging

Transmit and Receive Cell Interface Features

• Provides a 50 MHz, 8-bit, slave UTOPIA Level 2 interface (conforming to the ATM Forum standard specification af-phy-0039.000)
• Features efficient, configurable, EDMA-driven transmit and receive operation
• Includes optimized HEC Header Sequence Generation / Verification

Planned Features

• ATM Adaptation Layer 2 (AAL2) Support
• PCI (32 bit, 33MHz) host interface compliant with the PCI Local Bus Specifications (v. 2.0) and supporting both bus-master and bus-slave access modes
• Additional flow control and QoS functions